1. Field of the Invention
The present invention relates generally to microelectronic fabrications having formed therein redistribution structures. More particularly, the present invention relates to methods for fabricating microelectronic fabrications having formed therein redistribution structures.
2. Description of the Related Art
Microelectronic fabrications are formed from microelectronic substrates over which are formed patterned microelectronic conductor layers which are separated by microelectronic dielectric layers.
In conjunction with various means and configurations for interconnecting microelectronic fabrications of various varieties, it is common in the art of microelectronic fabrication to employ integral to individual microelectronic fabrications terminal electrode structures at locations within the individual microelectronic fabrications where the individual microelectronic fabrications are to be interconnected. Such terminal electrode structures are typically formed integral to the individual microelectronic fabrications while employing various metallurgy layers, which under certain circumstances may include solder interconnection layers, to which the various means and configurations for interconnecting the microelectronic fabrications may be connected. Similarly, and in conjunction with terminal electrode structures within microelectronic fabrications, there is also often employed within microelectronic fabrications redistribution structures which provide for a geometric redistribution of electrical connection structures, such as terminal electrode structures, within microelectronic fabrications.
While terminal electrode structures are thus desirable and clearly essential within the art of microelectronic fabrication for effectively providing electrical interconnections for various varieties of microelectronic fabrications which may be fabricated within the art of microelectronic fabrication, and similarly redistribution structures often provide unique and significant advantages in the art of microelectronic fabrication when fabricating microelectronic fabrications, both terminal electrode structures and redistribution structures are nonetheless not entirely without problems in the art of microelectronic fabrication when fabricating microelectronic fabrications. In that regard, it is typically highly desirable within the art of microelectronic fabrication, but nonetheless not always readily achievable within the art of microelectronic fabrication, to provide within a microelectronic fabrication a terminal electrode structure, and in particular a redistribution structure, both of which are economically fabricated with optimal properties.
It is thus towards the goal of providing for use when fabricating a microelectronic fabrication a terminal electrode structure, and in particular a redistribution structure, economically fabricated with optimal properties that the present invention is directed.
Various configurations and materials have been disclosed within the art of microelectronic fabrication for fabricating, with desirable properties, various microelectronic fabrication structures within microelectronic fabrications for use within the art of microelectronic fabrication.
For example, Hoffman et al., in U.S. Pat. No. 5,455,387, discloses a semiconductor integrated circuit microelectronic fabrication packaging microelectronic fabrication wherein there may be employed within the semiconductor integrated circuit microelectronic fabrication packaging microelectronic fabrication a single sized lead frame while simultaneously employing within the semiconductor integrated circuit microelectronic fabrication packaging microelectronic fabrication different sized semiconductor integrated circuit microelectronic fabrication die. To realize the foregoing result, the semiconductor integrated circuit microelectronic fabrication packaging microelectronic fabrication employs interposed between a lead frame and a semiconductor integrated circuit microelectronic fabrication die a redistribution interposer structure intended to accommodate semiconductor integrated circuit microelectronic fabrication die of various sizes.
In addition, Hubacher, in U.S. Pat. No. 5,554,940, discloses a semiconductor integrated circuit microelectronic fabrication and a method for fabricating the semiconductor integrated circuit microelectronic fabrication, wherein the semiconductor integrated circuit microelectronic fabrication may be readily tested with a single probe card assembly independent of whether the semiconductor integrated circuit microelectronic fabrication is subsequently wire bonded, tape automated bonded or solder bump bonded. To realize the foregoing result, the semiconductor integrated circuit microelectronic fabrication employs when fabricating the semiconductor integrated circuit microelectronic fabrication and formed over a patterned bond pad layer within the semiconductor integrated circuit microelectronic fabrication a redistribution structure comprising: (1) a test pad layer at a location proximal to the patterned bond pad layer; and (2) a solder bump pad layer at a location removed from the test pad layer, wherein the test pad layer, the solder bump pad layer and the bond pad layer are all in electrical communication.
Finally, Bird et al., in U.S. Pat. No. 5,946,552, discloses a semiconductor integrated circuit microelectronic fabrication packaging substrate and a method for fabricating the semiconductor integrated circuit microelectronic fabrication packaging substrate, wherein the semiconductor integrated circuit microelectronic fabrication packaging substrate may be employed for packaging various similarly sized semiconductor integrated circuit microelectronic fabrication die which have otherwise distinct wiring requirements. To realize the foregoing result, the semiconductor integrated circuit microelectronic fabrication packaging substrate comprises: (1) a first layer which has formed thereupon a minimum of two series of bond pad layers which correspond with separate wire-out requirements of at least two semiconductor integrated circuit microelectronic fabrication die which may be further fabricated while employing the semiconductor integrated circuit microelectronic fabrication packaging substrate; and (2) a second layer connected to the first layer through a series of vias corresponding with the at least two series of bond pad layers, where the second layer comprises a redistribution structure which redistributes from the minimum of two series of bond pad layers electrical signals to a set of connector pins within the semiconductor integrated circuit microelectronic fabrication packaging substrate.
Desirable for use when fabricating microelectronic fabrications are additional methods and materials which may be employed for fabricating within microelectronic fabrications terminal electrode structures, and in particular redistribution structures, which are economically fabricated with optimal properties.
It is towards the foregoing objects that the present invention is directed.
A first object of the present invention is to provide a method for fabricating a redistribution structure for use within a microelectronic fabrication.
A second object of the present invention is to provide a method for fabricating a redistribution structure in accord with the first object of the present invention, wherein the redistribution structure is economically fabricated with optimal properties.
A third object of the present invention is to provide a method for fabricating a redistribution structure in accord with the first object of the present invention and the second object of the present invention, which method is readily commercially implemented.
In accord with the objects of the present invention, there is provided by the present invention a method for fabricating a redistribution structure for use when fabricating a microelectronic fabrication. To practice the method of the present invention, there is first provided a substrate. There is then formed over the substrate a patterned bond pad layer. There is also formed over the substrate and in electrical communication with the patterned bond pad layer a patterned redistribution layer, wherein the patterned redistribution layer is formed employing a plating method.
The present invention provides a method for fabricating a redistribution structure for use within a microelectronic fabrication, wherein the redistribution structure is economically fabricated with optimal properties. The present invention realizes the foregoing object by employing a plating method when fabricating a patterned redistribution structure for use within a microelectronic fabrication in accord with the present invention.
The method of the present invention is readily commercially implemented. As is illustrated within the Description of the Preferred Embodiment which follows, the present invention employs methods and materials as are otherwise generally known in the art of microelectronic fabrication, but employed within the context of specific process controls, process limitations and process sequencing to provide the present invention. Since it is thus a materials selection and process control which provides at least in part the present invention, rather than the existence of methods and materials which provides the present invention, the method of the present invention is readily commercially implemented.